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1 2164b?hirel?06/03 features ? PC755M8 risc miprocessor ? dedicated 1-megabyte ssram l2 cache, configured as 128k x 72 ? 21 mm x 25 mm, 255 ceramic ball grid array (cbga) ? maximum core frequency = 350 mhz ? maximum l2 cache frequency = 175 mhz ? maximum 60x bus frequency = 66 mhz description the PC755M8 multichip package is targeted for high-performance, space-sensitive, low-power systems and supports the following power management features: doze, nap, sleep and dynamic power management. the PC755M8 is offered in industrial and military temperature ranges and is well suited for embedded applications. screening this product is manufactured in full compliance with: ? cbga up screenings based on atmel standards ? full military temp erature range (t j = -55 c, +125 c) industrial temperature range (t j = -40 c, +110 c) ssram ssram PC755M8 risc microprocessor multichip package preliminary specification -site PC755M8 rev. 2164b?hirel?06/03
2 PC755M8 2164b?hirel?06/03 block diagram figure 1. PC755M8 microprocessor block diagram additional features - time base counter/decrementer - clock multiplier - jtag/cop interface - thermal/power management - performance monitor + + fetcher branch processing btic 64-entr y + x ? fpscr cr fpscr l2cr ctr lr bht data mmu instruction mmu not in the pc745 ea pa + x ? instruction unit unit instruction queue (6-w ord) 2 instructions reservation station reservation station reservation station integer unit 1 system register unit dispatch unit 64-bit (2 instructions) srs itlb (shadow) ibat array 32-kbyte i cache tags 128-bit (4 instructions) reservation station 32-bit floating-point unit rename buffers (6) fpr file 32-bit 64-bit 64-bit reservation station (2-entry) load/store unit (ea calculation) store queue gpr file rename buffers (6) 32-bit srs (original) dtlb dbat array 64-bit completion unit reorder buffer (6-entr y) tags 32-kbyte d cache 60x bus interface unit instruction fetch queue l1 cast out queue data load queue l2 controller l2 tags l2 bus interface unit l2 cast out queue 32-bit address bus 32-/64-bit data bus 17-bit l2 address bus 64-bit l2 data bus integ er unit 2 ssram ssram
3 PC755M8 2164b?hirel?06/03 major features this section summarizes features of th e PC755M8?s implementation of the powerpc ? architecture. major features of the PC755M8 are as follows: ? branch processing unit ? four instructions fetched per clock ? one branch processed per cycle (plus resolving 2 speculations) ? up to 1 speculative stream in execut ion, 1 additional speculative stream in fetch ? 512-entry branch history table (bht) for dynamic prediction ? 64-entry, 4-way set associative branch target instructi on cache (btic) for eliminating bran ch delay slots ? dispatch unit ? full hardware detection of dependenc ies (resolved in the execution units) ? dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point) ? serialization control (pre dispatch, postdispatch, execution serialization) ? decode ? register file access ? forwarding control ? partial instruction decode ? completion ? 6-entry completion buffer ? instruction tracking and peak completion of two instructions per cycle ? completion of instructions in program order while supporting out-of-order instruction execution, completion se rialization and all instruction flow changes ? fixed point units (fxus) that share 32 gprs for integer operands ? fixed point unit 1 (fxu1) ? multiply, di vide, shift, rotate, arithmetic, logical ? fixed point unit 2 (fxu2) ? shif t, rotate, arithmetic, logical ? single-cycle arithmetic, shifts, rotates, logical ? multiply and divide support (multi-cycle) ? early out multiply ? floating-point unit and a 32-entry fpr file ? support for ieee-754 standard single and double precision floating-point arithmetic ? hardware support for divide ? hardware support for denormalized numbers ? single-entry reservation station ? supports non-ieee mode fo r time-critical operations ? system unit ? executes cr logical instructions a nd miscellaneous system instructions ? special register transfer instructions
4 PC755M8 2164b?hirel?06/03 ? load/store unit ? one cycle load or store cache access (byte, half-word, word, double-word) ? effective address generation ? hits under misses (one outstanding miss) ? single-cycle unaligned access within double word boundary ? alignment, zero padding, sign extend for integer register file ? floating-point internal format conversion (alignment, normalization) ? sequencing for load/store multiples and string operations ? store gathering ? cache and tlb instructions ? big and little-endian byte addressing supported ? misaligned little-endian supported ? level 1 cache structure ? 32k, 32 bytes line, 8-way set a ssociative instruction cache (il1) ? 32k, 32 bytes line, 8-way se t associative data cache (dl1) ? cache locking for both instruction and data caches, selectable by group of ways ? single-cycle cache access ? pseudo least-recently used (plru) replacement ? copy-back or write through data cache (on a page by page basis) ? supports all powerpc memory coherency modes ? non-blocking instruction and data cache (one outstanding miss under hits) ? no snooping of instruction cache ? memory management unit ? 128-entry, 2-way set asso ciative instruction tlb ? 128-entry, 2-way set associative data tlb ? hardware reload for tlbs ? hardware or optional software tablewalk support ? 8-instruction bats and 8-data bats ? 8 sprgs, for assistance with software tablewalks ? virtual memory support for up to 4 hexabytes (2 52 ) of virtual memory ? real memory support for up to 4 gigabytes (2 32 ) of physical memory ? bus interface ? compatible with 60x processor interface ? 32-bit address bus ? 64-bit data bus, 32-bit mode selectable ? bus-to-core frequency multipliers of 2x , 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x supported ? selectable interface voltages of 2.5v and 3.3v. ? parity checking on both address and data buses ? power management ? low-power design with thermal requirements ? very similar to pc740/750 ? selectable interface voltage of 1.8v/2.0 v can reduce power in output buffers (compared to 3.3v)
5 PC755M8 2164b?hirel?06/03 ? three static power saving modes: doze, nap, and sleep ? dynamic power management ? testability ? lssd scan design ? ieee 1149.1 jtag interface ? integrated thermal management assist unit ? on-chip thermal sensor and control logic ? thermal management interrupt for software regulation of junction temperature
6 PC755M8 2164b?hirel?06/03 signal description figure 2. PC755M8 microprocessor signal groups l2pin_data l2pin_data l2pin_data l2pin_data l2 clk_out a l2we l2ce a0-16 l2clk_out b l2pin_data l2pin_data l2pin_data l2pin_ data l2zz PC755M8 dqa dqb dqc dqd k sgw se1 sa0-16 sa0-16 sgw se1 k dqa dqb dqc dqd ssram 1 ssram 2 ft sbd sbc sbb sba sw adsp adv se2 adsc se3 lbo g ft sbd sbc sbb sba sw adsp adv se2 adsc se3 lbo g l20v dd l20v dd l2dp0-3 dp0-3 l2dp4-7 dp0-3 zz zz u2 u1
7 PC755M8 2164b?hirel?06/03 figure 2. PC755M8 microprocessor signal groups (continued) br bg abb ts tt[0-4] ap[0-3] tbst ts1z[0-2] gbl wt ci aack artr y dbg dbwo dbb l2addr [16-0] l2data [0-63] l2dp [0-7] l2clk-out [a-b] l2we a[0-31] l2sync_out l2sync_in int smi mcp hreset ckstp_in ckstp_out sysclk, pll_cfg [0-3] 4 17 64 8 factory test jt ag:cop l2 cache l2 vsel address/ dat a l2 cache clock/control interrupts reset clock control test interface 1 1 2 1 1 1 1 1 1 5 3 1 1 1 1 1 32 4 5 3 1 1 1 1 1 1 d[0-63] d[p0-7] dbdis ta drtr y tea PC755M8 l2av dd l2v dd sreset 1 1 rsr v tben tlbisync qreq qack processor status control clk_out 1 1 1 1 1 1 1 1 v dd av dd l2ce l2zz 1 1 8 1 1 1 11 64 gnd ov dd voltdet address arbitration address start address bus transfer attribute address termination data arbitration data transfer data termination
8 PC755M8 2164b?hirel?06/03 detailed specification scope this drawing describes the specific requi rements for the PC755M8 microprocessor, in compliance with atmel standard screening. applicable documents 1. in accordance with mil-std-883: test methods and procedures for electronics. 2. in accordance with mil-prf-38535 append ix a: general specifications for microcircuits. requirements general the microcircuits are in accordance with the applicable documents and as specified herein. design and construction terminal connections depending on the package, the terminal con nections are shown in table 10, table 1 and figure 2. absolute maximum rating notes: 1. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and func- tional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: v in must not exceed ov dd or l2ov dd by more than 0.3v at any time including during power - on reset. 3. caution: l2ov dd /ov dd must not exceed v dd /av dd /l2av dd by more than 1.6v during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: v dd /av dd /l2av dd must not exceed l2ov dd /ov dd by more than 0.4v during no rmal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 3. table 1. absolute maximum ratings (1) characteristic symbol maximum value unit core supply voltage (4) v dd -0.3 to 2.5 v pll supply voltage (4) av dd -0.3 to 2.5 v l2 dll supply voltage (4) l2av dd -0.3 to 2.5 v processor bus supply voltage (3) ov dd -0.3 to 3.465 v l2 bus supply voltage (3) l2ov dd -0.3 to 3.465 v input voltage processor bus (2)(5) v in -0.3 to ov dd + 0.3v v l2 bus (2)(5) v in -0.3 to l2ov dd + 0.3v v jtag signals v in -0.3 to 3.6 v storage temperature range t stg -65 to 150 c
9 PC755M8 2164b?hirel?06/03 figure 3. overshoot/undershoot voltage the PC755M8 provides severa l i/o voltages to support both compatibility with existing systems and migration to future systems . the PC755M8 core voltage must always be provided at nominal 2.0v (see table 3 for actual recommended core voltage). voltage to the l2 i/os and processor interface i/os are provided through separate sets of supply pins and may be provided at the voltages sh own in table 2. the input voltage threshold for each bus is selected by sampling the state of the voltage select pins bvsel and l2vsel during operation. these signals must remain stable during part operation and cannot change. the ou tput voltage will swing from gnd to the maximum voltage applied to the ov dd or l2ov dd power pins. notes: 1. the input threshold settings above are different for all revisions prior to rev 2.8 (rev e). for more information, cont act your local atmel sales office. 2. caution: the input threshold selection must agree with the ov dd /l2ov dd voltages supplied. (l2) ov dd +20% (l2) ov dd +5% (l2) ov dd gnd - 1.0v gnd - 0.3v gnd v ih not to exceed 10% of t sysclk v il table 2. input threshold voltage setting (1)(2) part revision bvsel signal l2vsel signal processor bus interface voltage l2 bus interface voltage e 0 0 not available not available 0 1 not available 2.5v/3.3v 1 0 2.5v/3.3v not available 1 1 2.5v/3.3v 2.5v/3.3v
10 PC755M8 2164b?hirel?06/03 recommended operating conditions notes: 1. these are the recommended and tested operating conditions . proper device operation outsid e of these conditions is not guaranteed. 2. revisions prior to rev. 2.8 (rev. e) offered different i/o voltage support. 3. 2.0v nominal. 4. 2.5v nominal. 5. 3.3v nominal. table 3. recommended operating conditions (1) recommended value 300 mhz, 350 mhz characteristic symbol min max unit core supply voltage (3) v dd 1.9 2.10 v pll supply voltage (3) av dd 1.9 2.10 v l2 dll supply voltage (3) l2av dd 1.9 2.10 v processor bus supply voltage (2)(4)(5) bvsel = 1 ov dd 2.375 2.625 v 3.135 3.465 v l2 bus supply voltage (2)(4)(5) l2vsel = 1 l2ov dd 3.135 3.465 v input voltage processor bus v in gnd ov dd v l2 bus v in gnd l2ov dd v jtag signals v in gnd ov dd v die-junction temperature military temperature range t j -55 125 c industrial temperature t j -40 110 c
11 PC755M8 2164b?hirel?06/03 l2 cache control register (l2cr) the l2 cache control register, shown in figure 4, is a supervisor-level, implementation- specific spr used to configure and operate t he l2 cache. it is cleared by hard reset or power-on reset. figure 4. l2 cache control register (l2cr) the l2cr bits are described in table 4. l2e 0 1 2 3 4 6 7 8 9 10 1112 13 1415 16 171819 20 21 22 23 24 30 31 l2siz l2clk l2ram l2i l2oh 0 0 l2ctr l2pe l2do l2ctl l2ts l2sl l2byp l2io l2dro l2ip l2wt l2df l2cs reserved table 4. l2cr bit settings bit name function 0 l2e l2 enable ? enables l2 cache operation (including snooping) starting with the next transaction the l2 cache unit receives. before enabling the l2 cache, the l2 clo ck must be configured throug h l2cr[2clk], and the l2 dll must stabilize. all other l2cr bits must be set appropriately. the l2 cache may need to be invalidated globally. 1 l2pe l2 data parity generation and checking enable ? enable s parity generation and checking for the l2 data ram interface. when disabled, generated parity is always ze ros. l2 parity is supported by PC755M8, but is dependent on application. 2 - 3 l2siz l2 size ? should be set according to the size of the l2 data rams used. 11 1-mbyte ? setting for PC755M8 4 - 6 l2clk l2 clock ratio (core-to-l2 frequency divider) ? specifies the clock divider ratio based at the core clock frequency that the l2 data ram interface is to operate at. when thes e bits are cleared, the l2 clock is stopped and the on- chip dll for the l2 interface is disabled. for nonzero va lues, the processor generates the l2 clock and the on- chip dll is enabled. after the l2 clock ratio is chosen , the dll must stabilize before the l2 interface can be enabled. the resulting l2 clock frequency cannot be slow er than the clock frequency of the 60x bus interface. 000 l2 clock and dll disabled 001 1 010 1.5 011 reserved 100 2 ? setting for PC755M8 101 2.5 110 3 111 reserved 7 - 8 l2ram l2 ram type ? configures the l2 ram interface for the type of synchronous srams used: ? pipelined (register-register) synchronous burst srams that clock addresses in and clock data out the PC755M8 does not burst data into the l2 ca che, it generates an address for each access. 10 pipelined (register-register) synchrono us burst sram ? setting for PC755M8 9 l2do l2 data-only ? setting this bit enables data-only operation in the l2 cach e. for this operation, instruction transactions from the l1 instruction cache already cached in the l2 cache can hit in the l2, but new instruction transactions from the l1 instructio n cache are treated as cache-inhibi ted (bypass l2 cache, no l2 checking done). when both l2do and l2io are set, the l2 cache is effectively locked (cache misses do not cause new entries to be allocated but write hits use the l2).
12 PC755M8 2164b?hirel?06/03 10 l2i l2 global invalidate ? setting l2i invalidates the l2 cache globally by clearing the l2 bits including status bits. this bit must not be set while the l2 cache is enabled. see motorola ? user?s manual for l2 invalidation procedure. 11 l2ctl l2 ram control (zz enable) ? setting l2ctl enables the automatic operation of the l2zz (low-power mode) signal for cache rams. sleep mode is supported by the PC755M8 ? while l2ct l is asserted, l2zz asserts automatically when the device enters nap or sleep mode and negates automatica lly when the device exits nap or sleep mode. this bit should not be set when the device is in nap mode and snooping is to be performed through deassertion of qack . 12 l2wt l2 write-through ? setting l2wt selects write-through m ode (rather than the default write-back mode) so all writes to the l2 cache also write through to the 60x bus. for these writes, the l2 cache entry is always marked as exclusive rather than m odified. this bit must never be asserted after the l2 cache has been enabled as previously-modified lines can get remark ed as exclusive during normal operation. 13 l2ts l2 test support ? setting l2ts causes cache block pu shes from the l1 data cache that result from dcbf and dcbst instructions to be written only into the l2 cache and ma rked valid, rather than being written only to the 60x bus and marked invalid in the l2 cache in case of hit. this bit allows a dcbz/dcbf instruction sequence to be used with the l1 cache enabled to easily initialize the l2 cache with any address and data information. this bit also keeps dcbz instructions from being broadcast on the 60x and single-beat cacheable store misses in the l2 from being written to the 60x bus. 0: setting for the l2 test support as this bit is reserved for tests. 14 - 15 l2oh l2 output hold ? these bits configure out put hold time for address, data, and control signals driven to the l2 data rams. 00 least hold time - setting for PC755M8 16 l2sl l2 dll slow ? setting l2sl increases the delay of each ta p of the dll delay line. it is intended to increase the delay through the dll to accommodate slower l2 ram bus frequencies. 0: setting for PC755M8 because l2 ram interface is operated above 100 mhz. 17 l2df l2 differential clock ? this mode supports the diff erential clock requirements of late-write srams. 0: setting for PC755M8 because late-write srams are not used. 18 l2byp l2 dll bypass is reserved. 0: setting for PC755M8 19 - 20 ? reserved ? these bits are implemented but not used; keep at 0 for future compatibility. 21 l2io l2 instruction-only ? setting this bit enables instruction-only operation in th e l2 cache. for this operation, data transactions from the l1 data cache already cached in the l2 cache can hit in the l2 (including writes), but new data transactions (transactions that miss in the l2) from the l1 data cache are treated as cache-inhibited (bypass l2 cache, no l2 checking done). when both l2do and l2io are set, the l2 cache is effectively locked (cache misses do not cause new entries to be allocated bu t write hits use the l2). note that this bit can be programmed dynamically. 22 l2cs l2 clock stop ? setting this bit causes the l2 clocks to the srams to automatically stop whenever the mpc755 enters nap or sleep modes, and automatic ally restart when exiting those modes (including for snooping during nap mode). it operates by asynchronously gating off the l2clk_out [a:b] signals while in nap or sleep mode. the l2sync_out/sync_in path remains in operation, keep ing the dll synchronized. this bit is provided as a power-saving alternative to the l2ctl bit and its corresp onding zz pin, which may not be useful for dynamic stopping/restarting of the l2 interface from nap and sleep m odes due to the relatively long recovery time from zz negation that the sram requires. table 4. l2cr bit settings (continued) bit name function
13 PC755M8 2164b?hirel?06/03 power consideration power management the PC755M8 provides four power modes, se lectable by setting the appropriate control bits in the msr and hido registers. the four power modes are as follows: ? full-power: this is the default power state of the PC755M8. the PC755M8 is fully powered and the internal functional units operate at the full processor clock speed. if the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state wit hout affecting perf ormance, software execution, or external hardware. ? doze: all the functional units of the PC755M8 are disabled except for the time base/decrementer registers and the bus sno oping logic. when the processor is in doze mode, an external asynchronous inte rrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine check brings the PC755M8 into the full-power state. the PC755M8 in doze mode maintains the pll in a fully powered state and locked to the system external clock input (sysclk) so a transition to the full-power state take s only a few processor clock cycles. ? nap: the nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the pll in a powered state. the PC755M8 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or a machine check input (mcp). a return to full-power state from a nap state takes only a few processor clock cycles. when the processor is in nap mode, if qack is negated, the processor is put in doze mode to support snooping. ? sleep: sleep mode minimizes power consumpt ion by disabling all internal functional units, after which external system logic may disable the ppl and susclk. returning the PC755M8 to the full-power state requires the enabling of the ppl and sysclk, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft rese t, or a machine check input (mcp) signal after the time requir ed to relock the ppl. 23 l2dro l2 dll rollover ? setting this bit enables a potential roll over (or actual rollover) condition of the dll to cause a checkstop for the processor. a potentia l rollover condition occurs when the dll is selecting t he last tap of the delay line, and thus may risk rolling over to the first tap with one adjustment while in the process of keeping synchronized. such a condition is improper operation for th e dll, and, while this cond ition is not expected, it allows detection for added security. this bit should be set when the dll is first enabled (set with the l2clk bits) to detect rollover during initial synchronization. it could also be set when the l2 cache is enabled (with l2e bit) after the dll has achieved its initial lock. 24 - 30 l2ctr l2 dll counter (read-only) ? these bits indicate the cu rrent value of the dll counter (0 to 127). they are asynchronously read when the l2cr is read, and as such should be read at least twice with the same value in case the value is asynchronously caught in transition. th ese bits are intended to provide observability of where in the 128-bit delay chain the dll is at any given time. ge nerally, the dll operation should be considered at risk if it is found to be within a couple of taps of its beginning or end point (tap 0 or tap 128). 31 l2ip l2 global invalidate in progress (read only) ? see the motorola user's manual for l2 invalidation procedure. table 4. l2cr bit settings (continued) bit name function
14 PC755M8 2164b?hirel?06/03 power dissipation notes: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include ov dd ; av dd and l2av dd suppling power. ov dd power is system dependent, but is typically < 10% of v dd power. worst case power consumption, for av dd = 15 mw and l2av dd = 15 mw. 2. maximum power is measured at v dd = 2.1v while running an entirely cache-resident, contrived sequence of instructions whic h keep the execution units maximally busy. 3. typical power is an average value measured at v dd = av dd = l2av dd = 2.0v, ov dd = l2ov dd = 3.3v in a system, executing ty pical applications and benchmark sequences. table 5. power consumption v dd = av dd = 2.0 0.1v, ov dd = 3.3v 5% v dc , gnd = 0 v dc , 0 t j < 105 c processor (cpu) frequency/l2 frequency unit 300/150 mhz 350/175 mhz full-on mode typical (1)(3) 4.1 4.6 w maximum (1)(2) 6.7 7.9 w doze mode maximum (1)(2) 2.5 2.8 w nap mode maximum (1)(2) 1700 1800 mw sleep mode maximum (1)(2) 1200 1300 mw sleep mode-pll and dll disabled maximum (1)(2) 500 500 mw
15 PC755M8 2164b?hirel?06/03 electrical characteristics static characteristics notes: 1. nominal voltages; see table 3 for recommended operating conditions. 2. for processor bus signals, the reference is ov dd while l2ov dd is the reference for the l2 bus signals. 3. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk) and ieee 1 149.1 boundary scan (jtag) signals. 4. capacitance is periodically sampled rather than 100% tested. 5. the leakage is measured for nominal ov dd and v dd , or both ov dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or - 5%). table 6. dc electrical specifications at recomm ended operating conditions (see table 3) characteristic nominal bus voltage (1) symbol min max unit input high voltage (all inputs except syslck) (2)(3) 2.5 v ih 1.6 (l2) ov dd + 0.3 v 3.3 v ih 2 (l2) ov dd + 0.3 v input low voltage (all inputs except syslck) (2) 2.5 v il -0.3 0.6 v 3.3 v il -0.3 0.8 v sysclk input high voltage 2.5 kv ih 1.8 ov dd + 0.3 v 3.3 kv ih 2.4 ov dd + 0.3 v sysclk input low voltage 2.5 kv il -0.3 0.4 v 3.3 kv il -0.3 0.4 v input leakage current, (2)(3) v in = l2ov dd /ov dd i in ? 10 a hi-z (off-state) leakage current, (2)(3)(5) v in = l2ov dd /ov dd i tsi ? 10 a output high voltage, i oh = - 6 ma 2.5 v oh 1.7 ? v 3.3 v oh 2.4 ? v output low voltage, i ol = 6 ma 2.5 v ol ? 0.45 v 3.3 v ol ? 0.4 v capacitance, v in = 0v, f = 1 mhz (3)(4) c in ? 5 pf
16 PC755M8 2164b?hirel?06/03 dynamic characteristics after fabrication, parts are sorted by maximum processor core frequency as shown in table 7 and tested for conformance to the ac specifications for that frequency. these specifications are for 275, 300, 333 mhz pr ocessor core frequencies. the processor core frequency is determined by the bus ( sysclk) frequency and the settings of the pll_cfg[0-3] signals. parts are sold by maximum processor core frequency. clock ac specifications table 7 provides the clock ac timing specifications as defined in table 1. notes: 1. caution: the sysclk frequency and pll_cfg[0 - 3] settings must be chosen such th at the resulting sysclk (bus) fre- quency, cpu (core) frequency, and pll (v co) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0 - 3] signal description in table 12,? for valid pll_cfg[0 - 3] settings 2. rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable i/o bus interface levels. the minimum slew rate of 1v/ns is equivalent to a 2 ns maximum rise/fall time measured at 0.4v and 2.4v or a rise/fall time of 1 ns measured at 0.4v to 1.4v. 3. timing is guaranteed by design and characterization. 4. this represents total input jitter ? short te rm and long term combined and is guaranteed by design. 5. relock timing is guaranteed by design and characterization. pll - relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power - on reset sequence. this specification also applies when the pll has been disabled and subsequently re - enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll - relock time during the power - on reset sequence. figure 5. sysclk input timing diagram table 7. clock ac timing specifications at recommend ed operating conditions (see table 3) characteristic symbol maximum processor core frequency unit 300 mhz 350 mhz min max min max processor frequency (1) f core 200 300 200 350 mhz vco frequency (1) f vco 400 600 400 700 mhz sysclk frequency (1) f sysclk 25 100 25 100 mhz sysclk cycle time t sysclk 10 40 10 40 ns sysclk rise and fall time (2) t kr & t kf ? 2 ? 2 ns t kr & t kf ? 1 ? 1 ns sysclk duty cycle measured at ov dd /2 (3) t khkl /t sysclk 40 60 40 60 % sysclk jitter (3)(4) ? 150 ? 150 ps internal pll relock time (3)(5) ? 100 ? 100 s s ysclk vm vm vm kv ih kv il vm = midpoint voltage (ov dd /2 ) t sysclk t kr t kf t khkl
17 PC755M8 2164b?hirel?06/03 processor bus ac specifications table 8 provides the processor bus ac timing specifications for the PC755M8 as defined in figure 6 and figure 8. notes: 1. all input specifications are measured from the midpoint of the signal in questi on to the midpoint of the rising edge of the input sysclk. all output specifications are measur ed from the midpoint of the rising edg e of sysclk to the midpoint of the sig- nal in question. all output timings assume a purely resistive 50 ? load (see figure 7). input a nd output timings are measured at the pin; time - of - flight delays must be added for trace l engths, vias, and connectors in the system. 2. the symbology used for timing specifications herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (reference)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i ) reach the valid state (v) relative to the sysclk reference (k) going to the high (h) state or input setup time. and t khov symbolizes the time from sysclk(k) going highs) until outputs (o) are valid (v) or output valid time. input hold time can be read as the time that the input signa l (i) went invalid (x) with respect to the rising clock edge (kh) ? note the position of the refe rence and its state for inputs ? and output hold time can be read as the time from the rising edge (kh) until the output went inva lid (ox). for additional explana- tion of ac timing specifications in motorola powerpc micr oprocessors, see the application note ?understanding ac timing specifications for powerpc microprocessors.? 3. the setup and hold time is with re spect to the rising edge of hreset (see figure 7). 4. this specification is for configuration mode select on ly. also note that the hreset must be held asse rted for a minimum of 255 bus clocks after the pll re - lock time during the power - on reset sequence. 5. t sysclk is the period of the exter nal clock (sysclk) in nanoseconds (ns). the num bers given in this t able must be multiplied by the period of sysclk to compute the actu al time duration (in nanoseconds) of the paramete r in question. 6. mode select signals are bvsel, l2vsel, pll_cfg[0 - 3] 7. guaranteed by design and characterization. 8. bus mode select pins must remain stable during operation. changing the logic states of bvsel or l2vsel during operation will cause the bus mode voltage selection to change. changing the logic states of the pl l_cfg pins during operation will cause the pll division ratio selection to change. both of t hese conditions are considered outside the specification and are not supported. once hreset is negated the states of the bus mode selection pins mu st remain stable. table 8. processor bus mode selectio n ac timing specifications (1) at v dd = a v dd = 2.0v 100 mv; -55 t j +125 c, ov dd = 3.3v 165 mv and ov dd = 1.8v 100 mv and ov dd = 2.0v 100 mv parameter symbols (2) all speed grades unit min max mode select input setup to hreset (3)(4)(5)(6)(7) t mvrh 8 ? t sysclk hreset to mode select input hold (3)(4)(6)(7)(8) t mxrh 0 ? ns
18 PC755M8 2164b?hirel?06/03 figure 6. input/output timing diagram figure 7. ac test load figure 8. mode input timing diagram sysclk all inputs vm vm = midpoint voltage (ov dd /2 or v in /2 ) all output s vm (except ts , abb, artr y, d b b ) ts ,abb,db b artr y vm t ivkh t ixkh t khoe t khov t khox t khabpz t khov t khox t khoz t kharpz t khov t khox t kharp t khov t khoz ov dd /2 output z 0 = 50 ? r l = 50 ? hrese t mode signal s vm = midpoint voltage (ov dd /2) vm t mvrh t mxrh
19 PC755M8 2164b?hirel?06/03 ieee 1149.1 ac timing specifications table 9 provides the ieee 1149 .1 (jtag) ac timing specific ations as defined in figure 9, figure 10, figure 11, and figure 12. notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of tclk to the midpoint of the signal in ques- tion. the output timings are measured at the pins. all output timings assume a purely resistive 50 ? load (see figure 9). time - of - flight delays must be added for trace le ngths, vias, and connectors in the system. 2. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 3. non - jtag signal input timing with respect to tck. 4. non - jtag signal output timing with respect to tck. 5. guaranteed by design and characterization. figure 9. alternate ac test load for the jtag interface figure 10. jtag clock input timing diagram table 9. jtag ac timing specificat ions (independe nt of sysclk) (1) parameter symbol min max unit tck frequency of operation f tclk 0 16 mhz tck cycle time f tclk 62.5 ? ns tck clock pulse width measured at 1.4v t jhjl 31 ? ns tck rise and fall times t jr & t jf 0 2 ns trst assert time (2) ttrst 25 ? ns input setup times: (3) boundary - scan data tms, tdi t dvjh t ivjh 4 0 ? ? ns input hold times: (3) boundary - scan data tms, tdi t dxjh t ixjh 15 12 ? ? ns valid times: (4) boundary - scan data tdo t jldv t jlov ? ? 4 4 ns output hold times: (4) boundary - scan data tdo t jldv t jlov 25 12 ? ? ns tck to output high impedance: (4)(5) boundary - scan data tdo t jldz t jloz 3 3 19 9 ns ov dd /2 output z 0 = 50 ? r l = 50 ? tclk vm vm vm vm = midpoint voltage (ov dd /2 ) t tclk t jr t jf t jhjl
20 PC755M8 2164b?hirel?06/03 figure 11. trst timing diagram figure 12. boundary-scan timing diagram figure 13. test access port timing diagram trst t trst vm = midpoint voltage (ov dd /2) vm vm vm vm tck boundary boundary boundary data outputs data inputs data outputs vm = midpoint voltage (ov dd /2 ) t dxjh t dvjh t jldv t jldz input data vali d output t jldh data valid output data valid tck tdi, tms tdo vm = midpoint voltage (ov dd /2) tdo vm vm t ixjh t ivjh t jlov t jloz input data vali d output t jloh data valid output data valid
21 PC755M8 2164b?hirel?06/03 preparation for delivery packaging microcircuits are prepared for deliv ery in accordance with mil-prf-38535. handling mos devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. input protection devices have been designed in the chip to minimize the effect of static buildup. however, the following handling practices are recommended: ? devices should be handled on benche s with conductive and grounded surfaces. ? ground test equipment, tools and operator. ? do not handle devices by the leads. ? store devices in conduc tive foam or carriers. ? avoid use of plastic, rubber, or silk in mos areas. ? maintain relative humidity above 50 percent if practical.
22 PC755M8 2164b?hirel?06/03 figure 14. pin assignments substrate assembly underfill encapsulant view die side profile of the cbga package to indicate the direction of the top surface view ball assignments of the 255 cbga package as viewed from the top surface
23 PC755M8 2164b?hirel?06/03 . table 10. package pinout listing signal name pin number active i/o 2.0v (7) 3.3v (7) a[0 - 31] c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, j2, f15, h3, f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 high i/o ? ? aack l2 low input ? ? abb k4 low i/o ? ? ap[0 - 3] c1, b4, b3, b2 high i/o ? ? artry j4 low i/o ? ? av dd a10 ? ? 2.0v 2.0v bg l1 low input ? ? br b6 low output ? ? bvsel (4)(5)(6) b1 high input gnd 3.3v ci e1 low output ? ? ckstp_in d8 low input ? ? ckstp_out a6 low output ? ? clk_out d7 ? output ? ? dbb j14 low i/o ? ? dbg n1 low input ? ? dbdis h15 low input ? ? dbwo g4 low input ? ? dh[0 - 31] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, n8, r8, t8, n7, r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 high i/o ? ? dl[0 - 31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p3, n3, n4, r3 , t1, t2, p4, t3, r4 high i/o ? ? dp[0 - 7] m2, l3, n2, l4, r1, p2, m4, r2 high i/o ? ? drtry g16 low input ? ? gbl f1 low i/o ? ? gnd c5, c12, e3, e6, e8, e9, e11, e14, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 ? ? gnd gnd hreset a7 low input ? ? int b15 low input ? ? l1_tstclk (1) d11 high input ? ? l2_tstclk (1) d12 high input ? ? l2av dd l11 ? ? 2.0v 2.0v l2ov dd (8) e10, e12, m12, g1 2, g14, k12, k14 ? ? 2.0v 3.3v
24 PC755M8 2164b?hirel?06/03 notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the processor core. 3. internally tied to gnd in the bga packa ge to indicate to the power supply that a low-voltage processor is present. this sig- nal is not a power supply pin. l2vsel (4)(5)(6)(7) b5 high input (12) ? 3.3v lssd_mode (1) b10 low input ? ? mcp c13 low input ? ? nc (no - connect) c3, c6, d5, d6, h4 , a4, a5, a2, a3 ? ? ? ? ov dd (2) c7, e5, g3, g5, k3, k5, p7, p10, e07, m05, m07, m10 ? ? ? ? pll_cfg[0 - 3] a8, b9, a9, d9 high input ? ? qack d3 low input qreq j3 low output rsrv d1 low output smi a16 low input sreset b14 low input ? ? stck (10) b7 ? input ? ? stdi c8 ? input ? ? stdo j16 ? output ? ? stms (11) b8 input sysclk c9 ? input ? ? ta h14 low input ? ? tben c2 high input ? ? tbst a14 low i/o ? ? tck c11 high input ? ? tdi (6) a11 high input ? ? tdo a12 high output ? ? tea h13 low input ? ? tlbisync c4 low input ? ? tms (6) b11 high input ? ? trst (6) c10 low input ? ? ts j13 low i/o ? ? tsiz[0 - 2] a13, d10, b12 high output ? ? tt[0 - 4] b13, a15, b16, c14, c15 high i/o ? ? wt d2 low output ? ? v dd (2) f6, f8, f9, f11, g7, g10, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9 ? ? 2.0v 2.0v voltdet (3) f3 low output ? ? table 10. package pinout listing (continued) signal name pin number active i/o 2.0v (7) 3.3v (7)
25 PC755M8 2164b?hirel?06/03 4. to allow for future i/o voltage changes, provide the opt ion to connect bvsel and l2vsel independently to either ov dd (selects 3.3v interface) or to gnd (selects 2.0v interface). 5. uses one of 15 existing no-connects in PC755M8. 6. internal pull up on die. 7. ov dd supplies power to the processor bus, jtag, and all contro l signals except the l2 cache controls (l2ce, l2we, and l2zz); l2ov dd supplies power to the l2 cache interface (l2add r (0-16], l2data (0-63), l2dp{0-7] and l2sync-out) and the l2 control signals and the ssram power supplies; and v dd supplies power to the processor core and the pll and dll (after filtering to become av dd and l2av dd respectively). these columns serve as a reference for the nominal voltage supported on a given signal as selected by the bvsel/l2vsel pin configurations and the volt age supplied. for actual rec- ommended value of v in or supply voltages see recommended operating conditions. 8. uses one of 20 existing v dd pins in PC755M8, no board level design changes are necessary. for new designs of PC755M8 refer to pll power supply filtering. 9. l2ov dd for future designs that will require 2.ov l2 cache pow er supply ? compatible with existing design using PC755M8. 10. to disable ssram tap controllers without interfering with the normal operation of the devices, stck should be tied low (gnd) to prevent cl ocking the devices. 11. stdi and stms are internally pulled up and may be left unconnected. upon power-up the ssram devices will come up in a reset state which will not interfer e with the operation of the device. 12. not supported on this version table 11. package description package outline 21 x 25 mm interconnects 255 (16 x 16 ball array less one) pitch 1.27 mm maximum module height 3.90 mm ball diameter 0.8 mm
26 PC755M8 2164b?hirel?06/03 figure 15. package dimensions 255 ball grid array notes: 1. dimensions in millimeters and paranthetically in inches. 2. a1 corner is designated with a ball missing the array. t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bottom view top view 2.975 (0.117) ref 19.05 (0.750) bsc 1.27 (0.050) bsc 19.05 (0.750) bsc 0.975 (0.038) ref 0.80 (0.032) bsc a1 corner 21.21 (0.835) max 25.25 (0.994) max 3.14 (0.024) max 3.04 (0.119) max 0.152 (0.006) 2.20 (0.087) max 0.64 0.070 (0.025 0.003)
27 PC755M8 2164b?hirel?06/03 clock selection the PC755M8?s pll is configured by the pll_cfg[0-3] signals. for a given sysclk (bus) frequency, the pll conf iguration signals set the internal cpu and vco frequency of operation. the pll configuration for the PC755M8 is shown in figure 17 for an exam- ple of frequencies. notes: 1. pll_cfg[0:3] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference onl y. some pll configurations ma y select bus, core, or vco frequencies which are not useful , not supported, or not tested for by the PC755M8; se e ?clock ac specifications? on page 16. for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, th e pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is inte nded for factory use and emulator tool use only. note: the ac timing specifications given in this document do not apply in pll-bypass mode. 4. in pll off mode, no clocking occurs inside the PC755M8 regardless of the sysclk input. table 12. PC755M8 microprocessor pll configuration pll_cfg [0-3] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to-core multiplier core-to vco multiplier bus 33 mhz bus 50 mhz bus 66 mhz bus 75 mhz bus 80 mhz bus 100 mhz 0100 2x 2x ? ? ? ? ? 200 (400) 1000 3x 2x ? ? 200 (400) 225 (450) 240 (480) 300 (600) 1110 3.5x 2x ? ? 233 (466) 263 (525) 280 (560) 350 (700) 1010 4x 2x ? 200 (400) 266 (533) 300 (600) 320 (640) ? 0111 4.5x 2x ? 225 (450) 300 (600) 338 (675) 360 (720) ? 1011 5x 2x ? 250 (500) 333 (666) ? ? ? 1001 5.5x 2x ? 275 (550) ? ? ? ? 1101 6x 2x 200 (400) 300 (600) ? ? ? ? 0101 6.5x 2x 216 (433) 325 (650) ? ? ? ? 0010 7x 2x 233 (466) 350 (700) ? ? ? ? 0001 7.5x 2x 250 (500) ? ? ? ? ? 1100 8x 2x 266 (533) ? ? ? ? ? 0110 10x 2x 333 (666) ? ? ? ? ? 0011 pll off/bypass pll off, sysclk clocks core circui try directly, 1x bus-to-core implied 1111 pll off pll off, no core clocking occurs
28 PC755M8 2164b?hirel?06/03 system design information pll power supply filtering the av dd and l2av dd power signals are provided on the PC755M8 to provide power to the clock generation phase-locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal cl ock, the power supplied to the av dd input signal should be filtered of any noise in the 500 khz to 10 mhz resonant frequency range of the pll. a circuit similar to the one shown in figure 17 using surface mount capacitors with mini- mum effective series inductance (esl) is recommended. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacitors of equal value are recom- mended over a single large value capacitor. the circuit should be placed as close as possible to the av dd pin to minimize noise cou- pled from nearby circuits. an identical but separate circuit should be placed as close as possible to the l2av dd pin. it is often possible to route di rectly from the capacitors to the av dd pin, which is on the periphery of the 360 bga footprint, without the inductance of vias. the l2av dd pin may be more difficult to route but is proportionately less critical. figure 16. pll power supply filter circuit power supply voltage sequencing the notes in figure 18 contain cautions about the sequencing of the external bus volt- ages and core voltage of the PC755M8 (when they are different). these cautions are necessary for the long term reliability of the par t. if they are violated, the esd (electro- static discharge) protection diodes will be forward biased and excessive current can flow through these diodes. if the system power supply design does not control the volt- age sequencing, the circuit of figure 18 can be added to meet these requirements. the mur420 schottky diodes of figure 18 co ntrol the maximum potential difference between the external bus and core power supplies on power-up and the 1n5820 diodes regulate the maximum potential difference on power-down. figure 17. example voltage sequencing circuit v dd av dd (or l2av dd ) 10 ? 2.2 f 2.2 f gnd low esl surface mount capacitors 3.3v 2.0v murs320 1n5820 murs320 1n5820
29 PC755M8 2164b?hirel?06/03 decoupling recommendations due to the PC755M8?s dynamic power management feature, large address and data buses, and high operating frequencies, the PC755M8 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the PC755M8 system, and the PC755M8 itself require s a clean, tightly regulated source of power. therefore, it is recommended that the system designer plac e at least one decou- pling capacitor at each v dd , o v dd , and l2ov dd pin of the PC755M8. it is also recommended that these decoupling capacitors receive their power from separate v dd , (l2)ov dd and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should have a value of 0.01 f or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connection s are made along the length of the part. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , l2o v dd , and ov vplanes, to enable quick recharging of the smaller chip capacitors. these bulk ca pacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors ? 100-330 f (avx tps tant alum or sanyo oscon). connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level through a resistor . unused active low inputs should be tied to o v dd . unused active high inputs should be co nnected to gnd. all nc (no-connect) sig- nals must remain unconnected. power and ground connections must be made to all external v dd , o v dd , l2o v dd , and gnd pins of the PC755M8. output buffer dc impedance the PC755M8 60x and l2 i/o drivers are char acterized over process, voltage, and tem- perature. to measure z 0 , an external resistor is connected from the chip pad to (l2)ov dd or gnd. then, the value of each resistor is varied until the pad voltage is (l2)o v dd /2 (see figure 18). the output impedance is the average of tw o components, the resistances of the pull-up and pull-down devices. when data is held lo w, sw2 is closed (sw1 is open), and r n is trimmed until the voltage at the pad equals (l2)o v dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and r p is trimmed until the voltage at the pad equals (l2)o v dd /2. r p then becomes the resis- tance of the pull-up devices. no tag describes the driver impedance measurement circuit described above.
30 PC755M8 2164b?hirel?06/03 figure 18. driver impedance measurement circuit table 13 summarizes the signal impedance re sults. the driver impedance values were characterized at 0 c, 65 c, and 105 c. the impedance increases with junction temper- ature and is relatively un affected by bus voltage. pull - up resistor requirements the PC755M8 requires pull-up resistors (1 k ? ? 5 k ? ) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the processo r or other bus masters. these pins are ts , abb , aack , artry , dbb , dbwo , ta , tea , and dbdis . drtry should also be connected to a pull-up resistor (1 k ? ? 5 k ? ) if it will be used by the system; otherwise, this signal should be connected to hreset to select no-drtry mode. three test pins also require pull-up resistors (100 ? ? 1 k ? ). these pins are l1_tstclk, l2_tstclk, and lssd_mode . these signals are for factory use only and must be pulled up to ov dd for normal machine operati on. in addition, ckstp_out is an open-drain style output that requires a pull-up resistor (1 k ? ? 5 k ? ) if it is used by the system. during inactive periods on the bu s, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. since the processor must continually monitor these sig- nals for snooping, this float condition may cause additional power draw by the input receivers on the processor or by other receivers in the system. these signals can be pulled up through weak (10 k ? ) pull-up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw, but address bus pull-up resistors are not neccessary for proper device operation. the snooped address and transfer attribute inputs are: a[0:31], ap[0:3], tt[0:4], tbst , and gbl . table 13. impedance characteristics v dd = 2.0v, ov dd = 3.3v, t c = 0 - 105 c impedance processor bus l2 bus symbol unit rn 25-36 25-36 z 0 w rp 26-39 26-39 z 0 w (l2)ov dd ognd r p r n pad data sw1 sw2 (l2)ov dd
31 PC755M8 2164b?hirel?06/03 the data bus input receivers are normall y turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. other data bus receivers in the system, howeve r, may require pull-ups, or that those signals be other- wise driven by the system during inactive pe riods by the system. the data bus signals are: dh[0:31], dl[0 :31], and dp[0:7]. if 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their outputs will drive logic zeros when they would otherwise nor- mally be driven. for this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize poss ible output switching. if address or data parity is not used by th e system, and the respective parity checking is disabled through hid0, the input receivers fo r those pins are disa bled, and those pins do not require pull-up resistors and should be left unconnected by the system. if all par- ity generation is disabled through hid0, then a ll parity checking should also be disabled through hid0, and all parity pins may be left unconnected by the system. jtag configuration signals figure 19. suggested trst connection figure 20. cop connector diagram pc755 hreset hreset trst from target board sources cop head er 2 k ? qac k qack 2 k ? 3 ck stp_out 13 9 5 1 6 10 2 top view 15 11 7 16 12 8 4 key no pi n hreset sreset tm s run/st op tck tdi tdo ground trst vdd_sense pins 10, 12 and 14 are no-connects. pin 14 is not physically pres ent qack chkstp_ in
32 PC755M8 2164b?hirel?06/03 boundary scan testing is enabled throug h the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification but is provid ed on all powerpc implementa- tions. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power- on reset performance will be obtained if the trst signal is asserted during power-on reset. since the jtag interface is also used for accessing the common on-chip processor (cop) function of powerpc processors, simply tying trst to hreset isn?t practical. the common on-chip processor (cop) function of powerpc processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface con- nects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the proce ssor. if the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset si gnals must be merged into these signals with logic. the arrangement shown in fi gure 19 allows the cop to independently assert hreset or trst , while insuring that th e target can drive hreset as well. the pull-down resis- tor on trst ensures that the jtag scan chain is initialized during power-on if a jtag interface cable is not attached; if it is, it is responsible for driving trst when needed. table 14. cop pin definitions pins signal connection special notes 1 tdo tdo 2 qack qack a dd 2k pull-down to ground. must be merged with on - board qack , if any. 3 tdi tdi 4 trst trst a dd 2k pull-down to ground. must be merged with on - board qack , if any. see figure 19. 5 run/stop no connect used on 604e; leave no - connect for all other processors. 6 vdd_sense vdd a dd 2k pull-up to ov dd (for short circuit li miting protection only). 7 tck tck 8 ckstp_in ckstp_in optional. a dd 10k pull-up to ovdd. used on several emulator products. useful for checkstopping the processor from a logic analyzer of other external trigger. 9 tms tms 10 n/a 11 sreset sreset merge with on - board sreset, if any. 12 n/a 13 hreset hreset merge with on - board hreset 14 n/a key location; pin should be removed. 15 ckstp_out ckstp_out a dd 10k pull-up to ovdd. 16 ground digital ground
33 PC755M8 2164b?hirel?06/03 the cop header shown in figure 20 adds many benefits ? breakpoints, watchpoints, register and memory examination/modifi cation and other standard debugger features are possible through this interface ? and can be as inexpensive as an unpopulated foot- print for a header to be added when needed. system design information the cop interface has a standard header for connection to the targ et system, based on the 0.025? square-post 0.100? centered header assembly (often called a ?berg? header). the connector typically has pin 14 removed as a connector key, as shown in figure 20. definitions life support applications these products are not designed for use in lif e support appliances, devices, or systems where malfunction of these pr oducts can reasonably be expect ed to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nity atmel for any damages resulting from such improper use or sale. datasheet status validity objective specification this datasheet contains targ et and goal specification for discussion with customer and application validation. before design phase. target specification this datasheet contains target or goal specification for product development. valid during the design phase. preliminary specification site this datasheet contains prel iminary data. additional data may be published later; could include simulation result. valid before characterization phase. preliminary specification site this datasheet contains also characterization results. valid before the industrialization phase. product specification this datasheet contains final product specification. valid for production purpose. limiting values limiting values given are in accordance with the absolute maximu m rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sect ions of the specification is not implied. exposure to limitin g values for extended periods may affect device reliability. application information where application information is given, it is advi sory and does not form part of the specification.
34 PC755M8 2164b?hirel?06/03 ordering information note: for availability of different vers ions, contact your atmel sales office. pc 755 m g l x m prefix type multichip package 8 package: g: cbga prototype (x) 300 revision level (1) e: rev. 2.8 temperature m: -55c, +125c v: -40c, +110c l2 cache density 8 mbits: 128k x 72 ssram bus divider (to be confirmed) l: any valid pll configuration core frequency 300: 300 mhz/150 l2 cache 350: 350 mhz/175 mhz l2 cache
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